How to order DesignArt Networks products ?

 We do not believe in "one-size-fits-all" solutions – and will treat your product request  in the context of your specific requirements. For a more detailed description of our product offering and engagement process, feel free to read the sections below.

 Or just contact us!

» Product Evaluation and Trial Cycles – Reference Designs and Evaluation Kits

 We are constatly expanding our interoperability with external partners, based on a growing family of reference designs. Based on these designs we are offering a complete evaluation kit program to interested vendors, a packaged program comprised of installation, test support and training services, as well as reference design boards pre-loaded with the desired SW-pack. Evaluation kits are fully functional product implementations - ready for immediate field trials.

 Vendors have been able to integrate our HW/SW reference designs with their OAM&P system – and move to field trials within just weeks or a few months. This allows prospective customers to gain mindshare with target operators, while gathering field-based feed-back to establish feature, price or performance requirements.

 Customers can rest assured, that even off-the-shelf DesignArt SW packs already support a plethora of differentiated features, simply not available in any competing product design, the most highly anticipated feature being high-capacity, in-band self-backhaul - but there are many more.

» Product Implementation Cycle – SW Packs and Open Platform SDK

 The premise of DesignArt is to deliver open SoC platforms to the market place – a combination of SoC silicon chips, application specific SW packs and fully functional reference designs. This enables the fastest time-to-market in the industry, based on low-cost, yet leading feature and performance positioning.

 Vendors have two fundamental options - integration of the DAN SoC with an external host processor (single-chip baseband architecture), or the integration of all SW applications with the embedded application processing layer (single-chip base station architecture). 

 Most prudent might be a step-by-step approach, beginning with an external host processor, targeting high-performance market segments, such as micro cells - then further integrating application and control plane SW layers with the open SoC platform, targeting compact and low-cost market segments, such as indoor pico or femto cells (while further cost-reducing the micro cell product line, of course).

 All SW packs include DesignArt's open SoC platform SDK; the SDK is SoC agnostic, thus establishing a single R&D framework across all of DesignArt's SoC products.

» Product Delivery Cycle – DesignArt SoC Platforms

 As discussed before, DesignArt customers enjoy the benefits of a fully integrated single-chip SoC platform architecture - the lowest-cost option for any target market specification.  Derivative SoC platform chips are available from DesignArt Networks, targeting specific market segment requirements - all based on an identical R&D design, implementation, and certification framework.

 The most flexible SoC platform available to date is the DAN2400, which scales from low-cost 2x2 Picocell applications, up to feature-rich and high-performance 6x6 macro cell sectors, supporting several SW options for the concurrent operation of integrated self-backhaul and relay functionality. The DAN2400 also supports DesignArt's dedicated backhaul SW pack, delivering a fully functional solution for high-performance PtP and PtMP backhaul systems.

 The DAN2200 is a derivative compact SoC platform for 2x2 RF configurations, targeting high-quantity customer premises oriented applications - such as femtocells, indoor repeaters, or high-capacity CPE segments. A fully integrated base station solution, the DAN2200 provides non-blocking performance for up to 25 simultaneous subscriber sessions - and includes local switching capability for home networking applications. The limitation in subscriber sessions comes with a tremendous benefit - as it frees up application level processor capacity for the integration of networking and home gateway application SW, fully eliminating the need for an external CPU.